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Hardware verification languages
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#	Item
171	Electronic Communications of the EASST No \volume defined! No \volumetitle defined! Verification of Railway Interlockings in Scade Add to Reading List Source URL: www-compsci.swan.ac.uk Language: English - Date: 2012-10-25 14:18:24 Science Formal methods Technology Formal sciences Esterel Technologies Railway signalling Lustre Interlocking Model checking Hardware description languages Synchronous programming languages Electronic engineering
172	PINAPA: An Extraction Tool for SystemC Descriptions of Systems-on-a-Chip ∗† Matthieu Moy [removed] Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2005-09-08 19:36:32 Logic design Electronic design automation SystemC Transaction-level modeling NCSim CPU design E Verilog VHDL Electronic engineering Hardware description languages Hardware verification languages
173	Designing, Verifying and Building an Advanced L2 Cache Sub-‐System using SystemC Designing, Verifying and Building an Advanced L2 Cache S Add to Reading List Source URL: events.dvcon.org Language: English - Date: 2012-02-07 19:56:23 Hardware verification languages SystemC E VHDL High-level synthesis CPU cache Forte Design Systems System on a chip Field-programmable gate array Electronic engineering Electronic design automation Hardware description languages
174	sutherland-hdl_workshops.fm Add to Reading List Source URL: www.sutherland-hdl.com Language: English - Date: 2012-11-02 18:47:30 Hardware verification languages SystemVerilog E Verilog Universal Verification Methodology Open Verification Methodology VHDL Intelligent verification Electronic engineering Electronic design automation Hardware description languages
175	sutherland-hdl_workshops.fm Add to Reading List Source URL: www.sutherland-hdl.com Language: English - Date: 2012-11-02 18:47:30 Electronic design automation Universal Verification Methodology E SystemVerilog University of Vermont Verilog Electronic engineering Hardware verification languages Hardware description languages
176	sutherland-hdl_workshops.fm Add to Reading List Source URL: www.sutherland-hdl.com Language: English - Date: 2012-11-02 18:47:30 Digital electronics Hardware verification languages Logic design SystemVerilog Verilog Synopsys E Verilator Flow to HDL Electronic engineering Electronic design automation Hardware description languages
177	sutherland-hdl_workshops.fm Add to Reading List Source URL: www.sutherland-hdl.com Language: English - Date: 2012-11-02 18:47:30 Hardware description languages Logic in computer science SystemVerilog Verilog E Formal verification Verification Synopsys Assertion Electronic engineering Electronic design automation Hardware verification languages
178	LNCS[removed]Second Competition on Software Verification Add to Reading List Source URL: www.sosy-lab.org Language: English - Date: 2013-10-11 06:59:10 Data management Model checking SystemC Benchmark Verilog BLAST model checker Standard Performance Evaluation Corporation Parallel computing Abstraction Electronic engineering Hardware description languages Electronic design automation
179	Qucs Report Book Technical reports and descriptions Add to Reading List Source URL: qucs.sourceforge.net Language: English - Date: 2013-11-22 08:10:48 Hardware description languages Logic design Quite Universal Circuit Simulator Verilog Hardware verification languages E Logic simulation SmartSpice Electronic engineering Electronic design automation Digital electronics
180	DVCon-2012_What-is-new-in-SystemVerilog-2012.fm Add to Reading List Source URL: www.sutherland-hdl.com Language: English - Date: 2012-11-02 18:47:29 Hardware description languages SystemVerilog Verilog Universal Verification Methodology E SV Integrated circuit design Generic programming Type system Electronic engineering Hardware verification languages Electronic design automation

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